Analyst lists 7 reasons why China CXMT’s claims don’t threaten Micron and Sandisk

Investing.com -- China's CXMT is claiming it will introduce a DDR5 RDIMM using a one-third smaller 4F-squared cell design by year-end, but Mizuho TMT specialist Jordan Klein says the announcement changes nothing for investors in Micron, SanDisk, SK Hynix, or Samsung Electronics.

"I would not be selling or in a panic if I owned MU, SNDK, SKHY or Samsung over comments yesterday by CXMT sr mgmt. about their new advanced DDR5 design roadmap. To me this changed nothing near term. Something to watch and monitor closely, but that is about it," Klein wrote in a note to clients.

The CXMT roadmap centers on a DDR5 RDIMM that uses a 4F-squared cell architecture combined with a vertical surrounding gate transistor, targeted for product introduction by the end of 2026.

The proposed cell would be roughly one-third smaller than the 6F-squared geometry used in current DDR5 designs, according to Mizuho's summary of CXMT's claims.

Klein laid out seven reasons why the announcement falls well short of a competitive threat. The most pointed is a timeline mismatch: Samsung's reported mass-production target for comparable 4F-squared DRAM technology is 2028, versus CXMT's stated end-of-2026 product introduction.

Klein argues those milestones cannot be compared directly. "A year-end product introduction can't be directly compared with Samsung's reported 2028 mass-production target. A launch doesn't establish manufacturing maturity, yields, or cost competitiveness," he wrote.

On the supply-glut concern that rattled some memory investors, Klein is equally skeptical. "CXMT hasn't shown mass-production success or verified yields and performance for its 4F² products, so it's premature to assume an imminent supply glut," he noted.

CXMT has not released complete specifications, verified yields, customer qualification results, or commercial-scale shipment commitments for the 4F-squared server RDIMM.

Klein also pushed back on the assumption that a smaller cell size automatically translates to lower chip cost, noting that process complexity, yields, and integration all factor into the final cost equation — areas where CXMT has yet to demonstrate competitive parity.

He further stressed that the product in question is conventional server DRAM, not High Bandwidth Memory (HBM), the stacked memory architecture central to AI accelerator racks built around GPUs and ASICs.